With scale-down and high integration of semiconductor chips or elements, the introduction of a shallow groove isolation (SGI), of a type in which an insulating film is embedded inside each groove defined in a silicon substrate, is proceeding to provide a device isolation structure that serves as an alternative to a local oxidization of silicon (LOCOS) method.
The above-described shallow groove isolation is considered to be advantageous from the point of view of ensuring sub-threshold characteristics and reduction in junction leakage and a backgate effect, as compared with the LOCOS method, because (a) the device isolation interval or space can be reduced, (b) it is easy to control the film thickness for device isolation and set a field reverse voltage, and (c) an inversion preventive layer can be separated from a diffused layer and a channel region by separately implanting an impurity in side walls of the inside of each groove and the bottom thereof.
A common method for forming the shallow groove isolation is as follows: First of all, a silicon substrate is subjected to thermal oxidation and a thin silicon oxide film is formed on the surface thereof. Thereafter, a silicon nitride film is deposited thereabove by a CVD (Chemical Vapor Deposition) method. Next, each silicon nitride film lying in a device isolation region is removed by dry etching using a photoresist film as a mask. Thereafter, trenches or grooves are defined in the substrate by dry etching with the silicon nitride films being left in each active region as masks.
Next, a thick silicon oxide film is deposited on the substrate, including the interiors of the grooves, by the CVD method. Thereafter, the substrate is subjected to a thermal process, and the silicon oxide films embedded inside the grooves are elaborately densified. Thereafter, the silicon oxide films above the silicon nitride films are removed by a polishing process, such as etchback or chemical mechanical polishing (CMP) or the like, and the unnecessary silicon nitride films are then removed, whereby shallow groove isolations are completed. Shallow groove isolations are discussed, for example, in Japanese Laid-Open Patent Application No. Hei 02-260660, No. Hei 04-303942, No. Hei 08-97277 etc.